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Overview Block Diagram External Ports Processor
Debuggers
Interrupt Controllers
Busses
axi4lite_0 microblaze_0_dlmb microblaze_0_ilmb Memory
Memory Controllers
microblaze_0_d_bram_ctrl microblaze_0_i_bram_ctrl Peripherals
axi_timer_0 logsys_axi_eth_if_0 logsys_axi_sp6_simpleio_0 logsys_axi_spi_if_0 IP
proc_sys_reset_0 Timing Information |